Because of the continuously increasing number of devices and circuits fabricated in an integrated circuit chip, there has been an ever increasing demand placed on the substrate for mounting such chips. Particularly, in a ceramic substrate having on its mounting surface at least two patterned metallization layers separated by a layer of insulating material, wherein one metallization layer including signal conductors for connecting the chip to the substrate lead pins and the other reference voltage conductors, more and more problems arise with the signal conductors. As a result of the close proximity of the signal conductors required to accommodate the high integration density of the circuit chips, inductive coupling can arise between them. Additionally, as a result of the thin insulating layer used to separate the planes, capacitive coupling can arise between the signal conductors of one plane and the reference voltage conductors of the other plane. These inductive and capacitive coupling effects can result in the spurious circuit performance which can render the chip and substrate combination commercially unacceptable.
The reasons for these problems becomes more apparent when the dimensions for a mounting substrate of the type described are considered. For example, substrate signal conductors typically have a width of 0.1 mm or less. Additionally, the spacing between signal conductors is typically between 2.5 and 0.1 mm or less. Further, the thickness of the insulating layer is typically 1 to 2 .mu.m. With such dimensioning, the effects of inductive coupling between signal conductors and capacitive coupling of the signal conductors and the reference plane metallization are no longer negligible. As would be apparent to those skilled in the art, such potential for parasitic circuits if left unchecked could adversely affect the performance of the mounted chip.